The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. In particular, the invention provides a method and device for monitoring various steps during the manufacturing of integrated circuits. Merely by way of example, the invention has been applied to measuring characteristics, such as dimensions, associated with trenching, etching, and/or growth process of a partially processed semiconductor for the manufacture of integrated circuits. More particularly, the invention provides a method for manufacturing integrated circuits using a monitoring technique for determining spatial dimensions of features, including trenches, and other features and the like. But it would be recognized that the invention has a much broader range of applicability. For example, an embodiment of the present invention provides a method for measuring capacitance of a partially processed integrated circuit.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is the conventional method used to measure various characteristics of partially process integrated circuits.
Fabrication of custom integrated circuits using chip foundry services has evolved over the years. Fabless chip companies often design the custom integrated circuits. Such custom integrated circuits require a set of custom masks commonly called “reticles” to be manufactured. A chip foundry company called Semiconductor Manufacturing International Corporation (SMIC) of Shanghai, China is an example of a chip company that performs foundry services. Although techniques for characterizing and evaluating partially or fully processed wafers are available, these techniques have many limitations.
As an example, it is often desirable to measure various characteristics (such as trench dimensions, electrical properties, etc.) of partially processed ICs during the manufacturing process. For example, dimensions of deep trenches (e.g., deep trenches for manufacturing of capacitors) are often a critical aspect of an IC. Various conventional techniques evaluate IC characteristics by dissecting partially processed ICs and examining the dissected ICs. Unfortunately, conventional techniques are often inadequate. That is, conventional techniques are often cumbersome, require manual cutting processes, are not efficient, and have high costs and other undesirable characteristics.
Therefore, an improved technique for processing semiconductor devices is desired.